Researchers at the University of Illinois Grainger College of Engineering have developed a new method for building three-dimensional (3D) silicon chips that could significantly extend the progress predicted by Moore’s Law.

Traditional chip miniaturization is approaching physical limits, but this breakthrough uses ultrathin silicon membranes and low-temperature manufacturing techniques to stack multiple layers of silicon circuits directly on top of one another.This approach enables faster communication between layers, higher device density, and reduced energy consumption.

The team fabricated three stacked layers of transistors using junctionless designs, achieving performance comparable to conventional silicon chips while remaining within the thermal limits required for monolithic 3D integration.

Unlike existing 3D chip technologies that bond completed wafers, this method produces layers sequentially on a single wafer, allowing nanometer-scale alignment and denser vertical interconnects.The process demonstrates high manufacturing yields of 98‒100%, strong uniformity, and scalability for additional layers.This advancement is particularly relevant for artificial intelligence and other data-intensive applications.

The research, published in Nature, highlights a practical path toward commercial production of true monolithic 3D silicon chips, with potential adoption by major semiconductor companies.Funding came from the National Science Foundation and industry partners including IBM, Intel, and TSMC.